Nisa Bostancı

PhD Student
@ ETH Zurich
email: nisa.bostanci
[at] safari.ethz.ch

Publications

2024

  • Ataberk Olgun, Yahya Can Tugrul, F. Nisa Bostanci, Ismail Emir Yuksel, Haocong Luo, Steve Rhyner, Abdullah Giray Yaglikci, Geraldo F. Oliveira, and Onur Mutlu,
    "ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation"
    Proceedings of the 33rd USENIX Security Symposium (USENIX Security), Philadelphia, PA, USA, August 2024.
    [arXiv version]
    [ABACuS Source Code (Officially Artifact Evaluated with All Badges)]
    Officially artifact evaluated as available, functional, and reproduced.
  • Ataberk Olgun, F. Nisa Bostanci, Geraldo F. Oliveira, Yahya Can Tugrul, Rahul Bera, A. Giray Yaglikci, Hasan Hassan, Oguz Ergin, and Onur Mutlu,
    "Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture"
    ACM Transactions on Architecture and Code Optimization (TACO), [online] June 2024.
    [arXiv version] [Sectored DRAM Source Code]
    [ACM Digital Library version]
  • Ismail Emir Yuksel, Yahya Can Tugrul, F. Nisa Bostanci, Geraldo F. Oliveira, A. Giray Yaglikci, Ataberk Olgun, Melina Soysal, Haocong Luo, Juan Gomez-Luna, Mohammad Sadrosadati, and Onur Mutlu,
    "Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis"
    Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), Brisbane, Australia, June 2024.
    [Slides (pptx) (pdf)]
    [arXiv version]
    [SiMRA-DRAM Source Code (Officially Artifact Evaluated with All Badges)]
    Officially artifact evaluated as both code and dataset available, reviewed and reproducible.
  • F. Nisa Bostanci, Ismail Emir Yuksel, Ataberk Olgun, Konstantinos Kanellopoulos, Yahya Can Tugrul, A. Giray Yaglikci, Mohammad Sadrosadati, and Onur Mutlu,
    "CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost"
    Proceedings of the 30th International Symposium on High-Performance Computer Architecture (HPCA), April 2024.
    [Slides (pptx) (pdf)]
    [arXiv version]
    [CoMeT Source Code (Officially Artifact Evaluated with All Badges)]
    Officially artifact evaluated as available, reviewed and reproducible.
  • Ismail Emir Yuksel, Yahya Can Tugrul, Ataberk Olgun, F. Nisa Bostanci, A. Giray Yaglikci, Geraldo F. Oliveira, Haocong Luo, Juan Gomez-Luna, Mohammad Sadrosadati, and Onur Mutlu,
    "Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis"
    Proceedings of the 30th International Symposium on High-Performance Computer Architecture (HPCA), April 2024.
    [Slides (pptx) (pdf)]
    [arXiv version]
    [FCDRAM Source Code]
  • Geraldo F. Oliveira, Ataberk Olgun, Abdullah Giray Yaglikci, F. Nisa Bostanci, Juan Gomez-Luna, Saugata Ghose, and Onur Mutlu,
    "MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing"
    Proceedings of the 30th International Symposium on High-Performance Computer Architecture (HPCA), April 2024.
    [Slides (pptx) (pdf)]
    [arXiv version]
    [MIMDRAM Source Code]
  • F. Nisa Bostanci*, Konstantinos Kanellopoulos*, Ataberk Olgun, A. Giray Yaglikci, Ismail Emir Yuksel, Nika Mansouri Ghiasi, Zulal Bingol, Mohammad Sadrosadati, and Onur Mutlu,
    "Amplifying Main Memory-Based Timing Covert and Side Channels using Processing-in-Memory Operations"
    arXiv preprint arXiv:2404.11284, April 2024.
    *Co-primary authors
  • Haocong Luo, Yahya Can Tugrul, F. Nisa Bostanci, Ataberk Olgun, A. Giray Yaglikci, and Onur Mutlu,
    "Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator"
    IEEE Computer Architecture Letters (CAL), 2024.
    [arXiv version]
    [Ramulator 2.0 Source Code]
  • 2023

  • Konstantinos Kanellopoulos, Hong Chul Nam, F. Nisa Bostanci, Rahul Bera, Mohammad Sadrosadati, Rakesh Kumar, Davide Basilio Bartolini, and Onur Mutlu,
    "Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources"
    Proceedings of the 56th International Symposium on Microarchitecture (MICRO), Toronto, ON, Canada, November 2023.
    [Slides (pptx) (pdf)]
    [arXiv version]
    [Victima Source Code (Officially Artifact Evaluated with All Badges)]
    Officially artifact evaluated as available, functional, reusable and reproducible.
    Distinguished artifact award at MICRO 2023.
  • Konstantinos Kanellopoulos, Rahul Bera, Kosta Stojiljkovic, F. Nisa Bostanci, Can Firtina, Rachata Ausavarungnirun, Rakesh Kumar, Nastaran Hajinazar, Mohammad Sadrosadati, Nandita Vijaykumar, and Onur Mutlu,
    "Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings"
    Proceedings of the 56th International Symposium on Microarchitecture (MICRO), Toronto, ON, Canada, November 2023.
    [Slides (pptx) (pdf)]
    [arXiv version]
    [Utopia Source Code]
  • 2022

  • Nandita Vijaykumar, Ataberk Olgun, Konstantinos Kanellopoulos, F. Nisa Bostanci, Hasan Hassan, Mehrshad Lotfi, Phillip B. Gibbons, and Onur Mutlu,
    "MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations"
    ACM Transactions on Architecture and Code Optimization (TACO), June 2022.
    [arXiv version]
    Presented at the 18th HiPEAC Conference, Toulouse, France, January 2023.
    [
    Slides (pptx) (pdf)]
    [Preliminary Talk Video (14 minutes)]
    [SAFARI Live Seminar Video (1 hour 26 minutes)]
    [MetaSys Source Code]
    Best paper award at HiPEAC 2023.
  • F. Nisa Bostanci, Ataberk Olgun, Lois Orosa, A. Giray Yaglikci, Jeremie S. Kim, Hasan Hassan, Oguz Ergin, and Onur Mutlu,
    "DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators"
    Proceedings of the 28th International Symposium on High-Performance Computer Architecture (HPCA), Virtual, April 2022.
    [Slides (pptx) (pdf)]
    [Short Talk Slides (pptx) (pdf)]
    [Talk Video (24 minutes)]
  • 2021

  • Ataberk Olgun, Minesh Patel, A. Giray Yaglikci, Haocong Luo, Jeremie S. Kim, F. Nisa Bostanci, Nandita Vijaykumar, Oguz Ergin, and Onur Mutlu,
    "QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips"
    Proceedings of the 48th International Symposium on Computer Architecture (ISCA), Virtual, June 2021.
    [Slides (pptx) (pdf)]
    [Short Talk Slides (pptx) (pdf)]
    [Talk Video (25 minutes)]
    [SAFARI Live Seminar Video (1 hr 26 mins)]

  • Index