Publications

2026

• Haocong Luo, Longda Zhou, Ataberk Olgun, Ismail Emir Yuksel, F. Nisa Bostanci, Zhigang Ji, Xing Wu, and Onur Mutlu,
  "Demystifying DRAM Read Disturbance: Bridging the Gap Between Experimental Characterization and Device-Level Modeling of RowHammer and RowPress Phenomena"
  arXiv preprint arXiv:2607.28233, 2026.
  [arXiv version]
• Ismail Emir Yuksel, F. Nisa Bostanci, Ataberk Olgun, and Onur Mutlu,
  "Memory-Centric Computing: Security Benefits and Challenges of Processing-in-DRAM"
  Proceedings of the 40th ACM International Conference on Supercomputing - Workshops (ICS Workshops), Belfast, Northern Ireland, United Kingdom, July 6-9, 2026.
  [arXiv version]
  [Slides (pptx) (pdf)]
• F. Nisa Bostanci, Haocong Luo, Ataberk Olgun, Maria Makeenkova, Geraldo F. Oliveira, A. Giray Yaglikci, and Onur Mutlu,
  "Extended Abstract: Re-Evaluating the Real-System Modeling Accuracy of Ramulator 2.0"
  Proceedings of the 40th ACM International Conference on Supercomputing - Workshops (ICS Workshops), Belfast, Northern Ireland, United Kingdom, July 6-9, 2026.
  [arXiv version]
  [Slides (pptx) (pdf)]
• Ataberk Olgun, Haocong Luo, Ismail Emir Yuksel, F. Nisa Bostanci, A. Giray Yaglikci, and Onur Mutlu,
  "A Modern Large-Scale Memory Characterization Laboratory"
  Proceedings of the 40th ACM International Conference on Supercomputing - Workshops (ICS Workshops), Belfast, Northern Ireland, United Kingdom, July 6-9, 2026.
  [arXiv version]
  [Slides (pptx) (pdf)]
  [DRAM Bender Source Code]
• Haocong Luo, F. Nisa Bostanci, Ataberk Olgun, Maria Makeenkova, Ziad Malik, Ipek Akdeniz, and Onur Mutlu,
  "Ramulator 2.1: A Composable Memory System Simulator for Modern DRAM Systems"
  Proceedings of the 40th ACM International Conference on Supercomputing - Workshops (ICS Workshops), Belfast, Northern Ireland, United Kingdom, July 6-9, 2026.
  [arXiv version]
  [Slides (pptx) (pdf)]
  [Tutorial Slides (pptx) (pdf)]
  [Ramulator 2.1 Source Code]
• Jikun Wang, Haocong Luo, Ataberk Olgun, Ismail Emir Yuksel, A. Giray Yaglikci, Yu Liang, F. Nisa Bostanci, Mohammad Sadrosadati, and Onur Mutlu,
  "ScaleDisturb: Exploiting Temporal Asymmetry to Amplify Read Disturbance in Modern DRAM Chips"
  Proceedings of the 56th Annual IEEE International Conference on Dependable Systems and Networks (DSN), Charlotte, NC, USA, June 22-25, 2026.
  [arXiv version]
  [Slides (pptx) (pdf)]
  [ScaleDisturb Source Code (Officially Artifact Evaluated with All Badges)]
  Officially artifact evaluated as both code and dataset available, reviewed and reproducible.
• Ataberk Olgun, F. Nisa Bostanci, Ismail Emir Yuksel, Haocong Luo, Minesh Patel, A. Giray Yaglikci, and Onur Mutlu,
  "DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips"
  arXiv preprint arXiv:2603.12435, 2026.
  [arXiv version]
• Harshita Gupta, Mayank Kabra, Jaewoo Park, Priyam Mehta, Phillip Widdowson, Tathagata Barik, F. Nisa Bostanci, Konstantinos Kanellopoulos, Juan Gomez-Luna, Antonio J. Peña, Mohammad Sadrosadati, and Onur Mutlu,
  "HE-PIM: Demystifying Homomorphic Operations on a Real-world Processing-in-Memory System"
  arXiv preprint arXiv:2605.12841, 2026.
  [arXiv version]
• Umut Baser, Ismail Emir Yuksel, F. Nisa Bostanci, Konstantinos Sgouras, Ataberk Olgun, Emre Hakan Demirli, Zhiheng Yue, Harsh Songara, Oguz Ergin, and Onur Mutlu,
  "In-DRAM Signature Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Off-The-Shelf DRAM Chips"
  Proceedings of the 56th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Disrupt Track (DSN Disrupt), Charlotte, USA, June 2026.
  [arXiv version]
  [Slides (pptx) (pdf)]
  [SiMRA-PUF Source Code]
• Daichi Tokuda, Ismail Emir Yuksel, Tatsuya Kubo, Ataberk Olgun, Haocong Luo, F. Nisa Bostanci, Jikun Wang, A. Giray Yaglikci, Shinya Takamaeda-Yamazaki, and Onur Mutlu,
  "PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems"
  Proceedings of the 53rd International Symposium on Computer Architecture (ISCA), Raleigh, NC, USA, June 2026.
  [arXiv version]
  [Slides (pptx) (pdf)]
• Haocong Luo, Ismail Emir Yuksel, Ataberk Olgun, F. Nisa Bostanci, Orhun Ecemis, A. Giray Yaglikci, and Onur Mutlu,
  "DejaVu: Why You Should Write to Your DRAM Rows Twice, Carefully"
  Proceedings of the 53rd International Symposium on Computer Architecture (ISCA), Raleigh, NC, USA, June 2026.
  [arXiv version]
  [Slides (pptx) (pdf)]
  [DejaVu Source Code (Officially Artifact Evaluated with All Badges)]
  Officially artifact evaluated as available, functional, and reproduced.
• Andreas Kosmas Kakolyris, F. Nisa Bostanci, Ataberk Olgun, Ismail Emir Yuksel, Harsh Songara, Konstantinos Sgouras, Umut Baser, Konstantinos Kanellopoulos, A. Giray Yaglikci, and Onur Mutlu,
  "ColumnKeeper: Efficient Solutions to the ColumnDisturb Vulnerability in DRAM-based Systems"
  Proceedings of the 53rd International Symposium on Computer Architecture (ISCA), Raleigh, NC, USA, June 2026.
  [arXiv version]
  [Slides (pptx) (pdf)]
  [ColumnKeeper Source Code (Officially Artifact Evaluated with All Badges)]
  Officially artifact evaluated as available, functional, and reproduced.
• F. Nisa Bostanci, Haocong Luo, Ataberk Olgun, Maria Makeenkova, Geraldo F. Oliveira, A. Giray Yaglikci, and Onur Mutlu,
  "Cleaning up the Mess: Re-Evaluating the Real-System Modeling Accuracy of Ramulator 2.0"
  Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Seoul, Republic of Korea, April 26-28, 2026.
  [arXiv version]
  [Slides (pptx) (pdf)]
  [Talk Video (YouTube)]
  [Cleaning up the Mess Source Code (Officially Artifact Evaluated with All Badges)]
  Officially artifact evaluated as available, functional, and reproduced.

2025

• F. Nisa Bostanci, Oguzhan Canpolat, Ataberk Olgun, Ismail Emir Yuksel, Konstantinos Kanellopoulos, Mohammad Sadrosadati, A. Giray Yaglikci, and Onur Mutlu,
  "Understanding and Mitigating Covert Channel and Side Channel Vulnerabilities Introduced by RowHammer Defenses"
  Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture (MICRO), Seoul, Republic of Korea, October 18-22, 2025.
  [arXiv version]
  [Slides (pptx) (pdf)]
  [LeakyHammer Source Code]
  Officially artifact evaluated as available, functional, and reproduced.
• Ismail Emir Yuksel, Ataberk Olgun, F. Nisa Bostanci, Haocong Luo, A. Giray Yaglikci, and Onur Mutlu,
  "ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems"
  Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture (MICRO), Seoul, Republic of Korea, October 18-22, 2025.
  [arXiv version]
  [Slides (pptx) (pdf)]
  One of the 12 computer architecture papers of 2025 selected as Top Picks by IEEE Micro.
• Ismail Emir Yuksel, Akash Sood, Ataberk Olgun, Oguzhan Canpolat, Haocong Luo, F. Nisa Bostanci, Mohammad Sadrosadati, A. Giray Yaglikci, and Onur Mutlu,
  "PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips"
  Proceedings of the 52nd Annual International Symposium on Computer Architecture (ISCA), Tokyo, Japan, June 21-25, 2025.
  [arXiv version]
  [Slides (pptx) (pdf)]
• Ismail Emir Yuksel, Ataberk Olgun, F. Nisa Bostanci, Oguzhan Canpolat, Geraldo F. Oliveira, Mohammad Sadrosadati, A. Giray Yaglikci, and Onur Mutlu,
  "In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips"
  Proceedings of the 43rd IEEE International Conference on Computer Design (ICCD), Richardson, TX, USA, November 10-12, 2025.
  [arXiv version]
  [Slides (pptx) (pdf)]
• Ataberk Olgun, F. Nisa Bostanci, Ismail Emir Yuksel, Oguzhan Canpolat, Haocong Luo, Geraldo F. Oliveira, A. Giray Yaglikci, Minesh Patel, and Onur Mutlu,
  "Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance"
  Proceedings of the IEEE International Symposium on High Performance Computer Architecture (HPCA), Las Vegas, NV, USA, March 1-5, 2025.
  [arXiv version]
  [Slides (pptx) (pdf)]
• Yahya Can Tugrul, A. Giray Yaglikci, Ismail Emir Yuksel, Ataberk Olgun, Oguzhan Canpolat, F. Nisa Bostanci, Mohammad Sadrosadati, Oguz Ergin, and Onur Mutlu,
  "Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions"
  Proceedings of the IEEE International Symposium on High Performance Computer Architecture (HPCA), Las Vegas, NV, USA, March 1-5, 2025.
  [arXiv version]
  [Slides (pptx) (pdf)]
  [PaCRAM Source Code (Officially Artifact Evaluated with All Badges)]
  Officially artifact evaluated as available, functional, and reproduced.
• Oguzhan Canpolat, A. Giray Yaglikci, Geraldo F. Oliveira, Ataberk Olgun, F. Nisa Bostanci, Ismail Emir Yuksel, Haocong Luo, Oguz Ergin, and Onur Mutlu,
  "Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance"
  Proceedings of the IEEE International Symposium on High Performance Computer Architecture (HPCA), Las Vegas, NV, USA, March 1-5, 2025.
  [arXiv version]
  [Slides (pptx) (pdf)]
  [Chronus Source Code (Officially Artifact Evaluated with All Badges)]
  Officially artifact evaluated as available, functional, and reproduced.
• Konstantinos Kanellopoulos, Konstantinos Sgouras, F. Nisa Bostanci, Andreas Kosmas Kakolyris, Berkin Kerim Konar, Rahul Bera, Mohammad Sadrosadati, Rakesh Kumar, Nandita Vijaykumar, and Onur Mutlu,
  "Virtuoso: Enabling Fast and Accurate Virtual Memory Research via an Imitation-based Operating System Simulation Methodology"
  Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2 (ASPLOS), Rotterdam, Netherlands, 30 March 2025 - 3 April 2025.
  [Slides (pptx) (pdf)]
  [Virtuoso Source Code]
  [Virtuoso webpage]

2024

• Ataberk Olgun, Yahya Can Tugrul, F. Nisa Bostanci, Ismail Emir Yuksel, Haocong Luo, Steve Rhyner, Abdullah Giray Yaglikci, Geraldo F. Oliveira, and Onur Mutlu,
  "ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation"
  Proceedings of the 33rd USENIX Security Symposium (USENIX Security), Philadelphia, PA, USA, August 2024.
  [arXiv version]
  [ABACuS Source Code (Officially Artifact Evaluated with All Badges)]
  Officially artifact evaluated as available, functional, and reproduced.
• Ataberk Olgun, F. Nisa Bostanci, Geraldo F. Oliveira, Yahya Can Tugrul, Rahul Bera, A. Giray Yaglikci, Hasan Hassan, Oguz Ergin, and Onur Mutlu,
  "Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture"
  ACM Transactions on Architecture and Code Optimization (TACO), [online] June 2024.
  [arXiv version] [Sectored DRAM Source Code]
  [ACM Digital Library version]
• Ismail Emir Yuksel, Yahya Can Tugrul, F. Nisa Bostanci, Geraldo F. Oliveira, A. Giray Yaglikci, Ataberk Olgun, Melina Soysal, Haocong Luo, Juan Gomez-Luna, Mohammad Sadrosadati, and Onur Mutlu,
  "Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis"
  Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), Brisbane, Australia, June 2024.
  [Slides (pptx) (pdf)]
  [arXiv version]
  [SiMRA-DRAM Source Code (Officially Artifact Evaluated with All Badges)]
  Officially artifact evaluated as both code and dataset available, reviewed and reproducible.
• F. Nisa Bostanci, Ismail Emir Yuksel, Ataberk Olgun, Konstantinos Kanellopoulos, Yahya Can Tugrul, A. Giray Yaglikci, Mohammad Sadrosadati, and Onur Mutlu,
  "CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost"
  Proceedings of the 30th International Symposium on High-Performance Computer Architecture (HPCA), April 2024.
  [arXiv version]
  [Slides (pptx) (pdf)]
  [Talk Video (YouTube)]
  [CoMeT Source Code (Officially Artifact Evaluated with All Badges)]
  Officially artifact evaluated as available, reviewed and reproducible.
• Ismail Emir Yuksel, Yahya Can Tugrul, Ataberk Olgun, F. Nisa Bostanci, A. Giray Yaglikci, Geraldo F. Oliveira, Haocong Luo, Juan Gomez-Luna, Mohammad Sadrosadati, and Onur Mutlu,
  "Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis"
  Proceedings of the 30th International Symposium on High-Performance Computer Architecture (HPCA), April 2024.
  [Slides (pptx) (pdf)]
  [arXiv version]
  [FCDRAM Source Code]
• Geraldo F. Oliveira, Ataberk Olgun, Abdullah Giray Yaglikci, F. Nisa Bostanci, Juan Gomez-Luna, Saugata Ghose, and Onur Mutlu,
  "MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing"
  Proceedings of the 30th International Symposium on High-Performance Computer Architecture (HPCA), April 2024.
  [Slides (pptx) (pdf)]
  [arXiv version]
  [MIMDRAM Source Code]
• F. Nisa Bostanci, Konstantinos Kanellopoulos, Ataberk Olgun, A. Giray Yaglikci, Ismail Emir Yuksel, Nika Mansouri-Ghiasi, Zulal Bingol, Mohammad Sadrosadati, and Onur Mutlu,
  "Revisiting Main Memory-Based Covert and Side Channel Attacks in the Context of Processing-in-Memory"
  Proceedings of the 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), Naples, Italy, June 23-26, 2025.
  [arXiv version]
  [Slides (pptx) (pdf)]
  [IMPACT Source Code (Officially Artifact Evaluated with All Badges)]
  Officially artifact evaluated as available, reviewed, and reproduced.
  *Co-primary authors
• Haocong Luo, Yahya Can Tugrul, F. Nisa Bostanci, Ataberk Olgun, A. Giray Yaglikci, and Onur Mutlu,
  "Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator"
  IEEE Computer Architecture Letters (CAL), 2024.
  [arXiv version]
  [Ramulator 2.0 Source Code]

2023

• Konstantinos Kanellopoulos, Hong Chul Nam, F. Nisa Bostanci, Rahul Bera, Mohammad Sadrosadati, Rakesh Kumar, Davide Basilio Bartolini, and Onur Mutlu,
  "Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources"
  Proceedings of the 56th International Symposium on Microarchitecture (MICRO), Toronto, ON, Canada, November 2023.
  [Slides (pptx) (pdf)]
  [arXiv version]
  [Victima Source Code (Officially Artifact Evaluated with All Badges)]
  Officially artifact evaluated as available, functional, reusable and reproducible.
  Distinguished artifact award at MICRO 2023.
• Konstantinos Kanellopoulos, Rahul Bera, Kosta Stojiljkovic, F. Nisa Bostanci, Can Firtina, Rachata Ausavarungnirun, Rakesh Kumar, Nastaran Hajinazar, Mohammad Sadrosadati, Nandita Vijaykumar, and Onur Mutlu,
  "Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings"
  Proceedings of the 56th International Symposium on Microarchitecture (MICRO), Toronto, ON, Canada, November 2023.
  [Slides (pptx) (pdf)]
  [arXiv version]
  [Utopia Source Code]

2022

• Ismail Emir Yuksel, Ataberk Olgun, Behzad Salami, F. Nisa Bostanci, Yahya Can Tugrul, A. Giray Yaglikci, Nika Mansouri-Ghiasi, Onur Mutlu, and Oguz Ergin,
  "TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs"
  arXiv preprint arXiv:2211.10894, 2022.
  [arXiv version]
• Nandita Vijaykumar, Ataberk Olgun, Konstantinos Kanellopoulos, F. Nisa Bostanci, Hasan Hassan, Mehrshad Lotfi, Phillip B. Gibbons, and Onur Mutlu,
  "MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations"
  ACM Transactions on Architecture and Code Optimization (TACO), June 2022.
  [arXiv version]
  Presented at the 18th HiPEAC Conference, Toulouse, France, January 2023.
  [Slides (pptx) (pdf)]
  [Preliminary Talk Video (14 minutes)]
  [SAFARI Live Seminar Video (1 hour 26 minutes)]
  [MetaSys Source Code]
  Best paper award at HiPEAC 2023.
• F. Nisa Bostanci, Ataberk Olgun, Lois Orosa, A. Giray Yaglikci, Jeremie S. Kim, Hasan Hassan, Oguz Ergin, and Onur Mutlu,
  "DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators"
  Proceedings of the 28th International Symposium on High-Performance Computer Architecture (HPCA), Virtual, April 2022.
  [Slides (pptx) (pdf)]
  [Short Talk Slides (pptx) (pdf)]
  [Talk Video (24 minutes)]

2021

• Ataberk Olgun, Minesh Patel, A. Giray Yaglikci, Haocong Luo, Jeremie S. Kim, F. Nisa Bostanci, Nandita Vijaykumar, Oguz Ergin, and Onur Mutlu,
  "QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips"
  Proceedings of the 48th International Symposium on Computer Architecture (ISCA), Virtual, June 2021.
  [Slides (pptx) (pdf)]
  [Short Talk Slides (pptx) (pdf)]
  [Talk Video (25 minutes)]
  [SAFARI Live Seminar Video (1 hr 26 mins)]