Nisa Bostanci

PhD Student @ ETH Zurich

I am currently a PhD student in Safari Research Group at ETH Zurich led by Prof. Onur Mutlu. I completed my BSc and Msc degrees in Computer Engineering at TOBB ETU under supervision of Prof. Oguz Ergin. I am broadly interested in computer architecture and tackling interesting problems of current and future systems. My recent work focuses on memory systems, particularly their security, reliability, and safety (robustness), and designing effective and efficient solutions to address robustness issues. Recently, I have been working on low cost and scalable RowHammer mitigation techniques to improve the robustness of DRAM-based computing systems. I am also interested in exploring the robustness of emerging computing paradigms and future systems, such as processing-in-memory, against vulnerabilities.

Before starting my PhD, I was a member of the Kasirga Microprocessors' Lab in TOBB ETU. Between the years of 2016 and 2022, I had the chance to lead and contribute to many exciting projects, including various RISC-V-based processor and microcontroller designs. At around the same time, I worked on extending a cycle-level DRAM simulator, Ramulator, with 1) a CPU instruction and memory request trace generator tool based on Intel Pin to alleviate overheads of simulating modern systems and 2) emerging memory technology models such as STT-RAM and PCM, enabling accurate simulations for these memory technologies.

Selected Paper Publications

For all publications please check my publications, or Google Scholar.

• "Revisiting Main Memory-Based Covert and Side Channel Attacks in the Context of Processing-in-Memory" in DSN 2025.
  F. Nisa Bostanci*, Konstantinos Kanellopoulos*, Ataberk Olgun, A. Giray Yaglikci, Ismail Emir Yuksel, Nika Mansouri Ghiasi, Zulal Bingol, Mohammad Sadrosadati, and Onur Mutlu.
  *Co-primary authors
• "CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost" in HPCA 2024.
  F. Nisa Bostanci, Ismail Emir Yuksel, Ataberk Olgun, Konstantinos Kanellopoulos, Yahya Can Tugrul, A. Giray Yaglikci, Mohammad Sadrosadati, and Onur Mutlu.
  
• "DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators" in HPCA 2022.
  F. Nisa Bostanci, Ataberk Olgun, Lois Orosa, A. Giray Yaglikci, Jeremie S. Kim, Hasan Hassan, Oguz Ergin, and Onur Mutlu.
  
• "Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance." in HPCA 2025.
  Ataberk Olgun, F. Nisa Bostanci, Ismail Emir Yuksel, A. Giray Yaglikci, Geraldo F. Oliveira, Haocong Luo, Oguzhan Canpolat, Minesh Patel, and Onur Mutlu.
  
• "ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation" in USENIX Security 2024.
  Ataberk Olgun, Yahya Can Tugrul, F. Nisa Bostanci, Ismail Emir Yuksel, Haocong Luo, Steve Rhyner, Abdullah Giray Yaglikci, Geraldo F. Oliveira, and Onur Mutlu.
  
• "Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture" in TACO 2024.
  Ataberk Olgun, F. Nisa Bostanci, Geraldo F. Oliveira, Yahya Can Tugrul, Rahul Bera, A. Giray Yaglikci, Hasan Hassan, Oguz Ergin, and Onur Mutlu.
  
• "Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis" in DSN 2024.
  Ismail Emir Yuksel, Yahya Can Tugrul, F. Nisa Bostanci, Geraldo F. Oliveira, A. Giray Yaglikci, Ataberk Olgun, Melina Soysal, Haocong Luo, Juan Gomez-Luna, Mohammad Sadrosadati, and Onur Mutlu.
  
• "Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator" in CAL 2024.
  Haocong Luo, Yahya Can Tugrul, F. Nisa Bostanci, Ataberk Olgun, A. Giray Yaglikci, and Onur Mutlu.
  
• "Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources" in MICRO 2023.
  Konstantinos Kanellopoulos, Hong Chul Nam, F. Nisa Bostanci, Rahul Bera, Mohammad Sadrosadati, Rakesh Kumar, Davide Basilio Bartolini, and Onur Mutlu.
  

Selected Talks

Last update: 2025-03-14